CHIPLIST 9.1 by Aad Offerman, 23-02-96

A. Offerman
Bonnweg 40
3137NE Vlaardingen
The Netherlands
010-4745386

Since there are a lot of questions about the differences between the various chips used in the IBM PC, IBM PC/XT, IBM PC/AT, IBM PS/2 and compatibles, this list, containing their CPUs and NPXs, has been compiled for the benefit of the net community. I hope it can answer some questions.

This list is the result of collecting many snippets of information from USENET News and data books. Furthermore, various contributors and others have helped to make this list to what it is today. Thank you all.

Any corrections, additions, or comments are welcome. Please reply by E-mail to:

offerman@einstein.et.tudelft.nl

The WWW HTML version of the latest chiplist is available at:

http://einstein.et.tudelft.nl/~offerman/chiplist.html

The original plain text version of this list is cross-posted about once every month to the following newsgroups:

The latest version of this list can also be obtained by anonymous FTP from:

rtfm.mit.edu /pub/usenet/news.answers/pc-hardware-faq/chiplist/
ftp.twi.tudelft.nl /pub/texts/chiplist/chiplist.asc

1 Introduction
1.1 Identification
1.2 Packages
1.3 Semiconductor processes
1.4 JEDEC (Joint Electronic Device Engeneering Council)
1.5 Manufacturers
1.5.1 Intel
1.5.2 AMD (Advanced Micro Devices)
1.5.3 IBM (International Bussiness Machines)
1.5.4 Chips & Technologies
1.5.5 Cyrix
1.5.6 Texas Instruments
1.5.7 NexGen
1.5.8 IIT (Integrated Information Technology)
1.5.9 Motorola
1.5.10 Apple
1.5.11 HP
1.5.12 DEC (Digital Equipment Corporation)
1.5.13 Renaissance Microsystems Inc.
1.6 Literature

3 NPX (Numerical Processor eXtension)
3.1 Introduction
3.2 Intel i8087 NPX
3.3 Intel i80287 NPX
3.4 AMD Am80287 NPX
3.4.1 AMD Am80C287 NPX
3.4.2 AMD Am80EC287 NPX
3.5 Cyrix Cx287 NPX
3.6 Intel i80187 NPX
3.7 Intel i80287XL NPX
3.8 Cyrix FasMath Cx82S87 NPX
3.9 IIT IIT-2C87 NPX
3.10 Intel i80387 NPX
3.10.1 Intel i80387 NPX
3.10.2 Intel i80387DX NPX
3.10.3 Intel i80387SX NPX
3.10.4 Intel i80387SL Mobile NPX
3.10.5 Intel i80X87SL Mobile NPX
3.11 Chips & Technologies SuperMath 38700 NPX
3.11.1 Chips & Technologies SuperMath 38700DX NPX
3.11.2 Chips & Technologies SuperMath 38700SX NPX
3.12 Cyrix 80387 NPX
3.12.1 Cyrix FasMath Cx83D87 NPX
3.12.2 Cyrix FasMath Cx387+ NPX
3.12.3 Cyrix FasMath EMC87 NPX
3.12.4 Cyrix FasMath 83S87 NPX
3.12.5 Cyrix Cx387DX NPX
3.12.6 Cyrix Cx387SX NPX
3.12.7 Cyrix Cx387 NPX announcements
3.13 IIT IIT-3C87 NPX
3.13.1 IIT IIT-3C87 NPX
3.13.2 IIT IIT-3C87SX NPX
3.13.3 IIT IIT-XC87DLX2 NPX
3.14 ULSI Math*Co 83C87 NPX
3.15 ULSI Math*Co 83S87 NPX
3.16 Weitek Abacus 1167 NPX
3.17 Weitek Abacus 3167 NPX
3.18 RISE 80387 NPX
3.19 Symphony Laboratories 80387 NPX
3.20 Cyrix Cx4C87DLC NPX
3.21 IIT IIT-4C87 NPX
3.21.1 IIT IIT-4C87DLC NPX
3.21.2 IIT IIT-4C87 NPX announcements
3.22 Intel i80487 NPX
3.22.1 Intel i80487SX NPX
3.22.2 Intel i80487 NPX
3.23 Cyrix Cx487S NPX
3.24 Weitek Abacus 4167 NPX

Credits

1 Introduction

1.1 Identification

Manufacturer: name and/or logo.
Part number.
Revision number, step level.
Date: often the week number and the year of manufacturing.

Memory chips:

capacity:
- 64, 256 kbit,
- 1, 4, 16 Mbit,
speed: 10, 15, 20, 40, 60, 70, 80, 100, 120, 150 ns.

Orientation: indicated by a hole or a dot; from this indication the pin numbering starts contra clock-wise with number 1.

For microprocessors at boot the chip mask revision number is often left in one of the control registers.

In the newer SL enhanced Intel i80486 CPUs (if bit 21 in EFLAGS can be toggled) and the Intel Pentium CPUs a CPUID instruction is available:

EAX=0:
- EAX: highest input value recognized by CPUID
- EBX-EDX: vendor ID string:
  - Intel: "GenuineIntel"
  - AMD: "AuthenticAMD"
  - Cyrix: "CyrixInstead"
  - NexGen: "NexGenDriven"
  - UMC: "UMC UMC UMC "
EAX=1:
- EAX:
  - bit 0-3: step level
  - bit 4-7: model
  - bit 8-11: family: 4: 486, 5: Pentium
  - bit 12-31: reserved
- EBX-ECX: reserved
- EDX (feature bits):
  - bit 0: on-chip FPU
  - bit 1-6: I/O Breakpoints available, Page Size extensions (single-level page table with 4 Mbyte pages), Time Stamp Counter available (RDTSC), Machine Specific Registers available (RDMSR/WRMSR)
  - bit 7: Machine Check Exception
  - bit 8: CMPXCHG8B instruction
  - bit 9-31: reserved

1.2 Packages

DIP (Dual In-line Package):

  o o o o o o o o

  o o o o o o o o

CERDIP (CERamic Dual In-line Package).

PQFP (Plastic Quad Flat Package): surface mounted.
SQFP (Shrink Quad Flat Package): surface mounted, thermally enhanced.

PLCC (Plastic Leaded Chip Carrier).

PGA (Pin Grid Array):

  o o o o o o o o
  o o o o o o o o
  o o         o o
  o o         o o
  o o         o o
  o o         o o
  o o o o o o o o
  o o o o o o o o

ZIP (Zigzag In-line Package):

  o o o o o o o o
   o o o o o o o o

DRAM (Dynamic Random Access Memory):

4116 16 k x 1 (1980),
4164 64 k x 1 (1982),
41256 256 k x 1 (1984),
411000 1 m x 1 (1987, 1988).

SIMM (Single In-line Memory Module) (Wang): contains a complete RAM bank. Mac SIMMs are only 8 bits wide; they don't contain a parity bit. However, there are Personal Computers around in which the RAM chips for parity checking are build-in on the motherboard, that need 8 bit SIMMs.

9-chip SIMM: 9 chips of 1 bit wide
8-chip SIMM: 8 chips of 1 bit wide (Mac)
3-chip SIMM: 2 chips of 4 bits wide and 1 chip of 1 bit wide or 3 chips of 3 bits wide
2-chip SIMM: 2 chips of 4 bits wide (Mac)

If the correct refresh is supplied SIMMs with a different number of chips and different speed can be used together.

SIP (Single In-line Package): contains a complete RAM bank.

The orientation of SIMMs and SIPs is indicated by a hole. Starting from this indication the numbering of the pins starts with number 1. Apart from the pins there is no difference at all between SIMMs and SIPs.

The normal SIMMs and SIPs have 30 pins/pads. There are also 36 pin SIMMs and SIPs. The extra pins are used for speed detection by the motherboard.

There are also 72 pin SIMMs. These are 32 bits and 4 parity bits wide. 4 pins are assigned for speed detection. They are mostly used in newer Personal Computers.
Capacity: 1, 2, 4, 8, 16 Mwords.

DIMM: 64 bit memory module.

1.3 Semiconductor processes

RTL (Resistor-Transistor Logic): SSI (Small Scale Integration).

DTL (Diode-Transistor Logic): SSI.

TTL (Transistor-Transistor Logic) (Texas Instruments, 1965): bipolar, SSI, MSI (Medium Scale Integration), LSI (Large Scale Integration).

7400 series: 0 - 70 C.
5400 series: -55 - 125 C (military).

5400, 7400: 10 ns propagation time,
54L00, 74L00: Low power: higher resistances, less dissipation: longer propagation time,
54H00, 74H00: High power: lower resistances, more dissipation: less sensitivity for noise,
54S00, 74S00: Schottky-clamped: faster switching by using Schottky diodes to prevent the transistors from saturation,
54LS00, 74LS00: Low power, Schottky-clamped,
54AS00, 74AS00: Advanced Schottky: faster switching, less dissipation,
54ALS00, 74ALS00: Advanced Low power Schottky.

I2L (Integrated Injection Logic) (1972): bipolar, LSI, VLSI (Very Large Scale Integration).

Vcc: 0.8 V.
Propagation time: 20 - 50 ns.
Speed-power: 0.5 pJ.

ECL (Emitter Coupled Logic, Current Mode Logic): bipolar.

Propagation time: 0.5 - 2 ns.
Dissipation: 3 - 10 times higher than TTL.

MOS (Metal Oxide Semiconductor): FET (Field-Effect Transistors).

Maximum frequency: 25 MHz.

PMOS (Positive-channel MOS): LSI, VLSI.

NMOS (Negative-channel MOS): LSI, PMOS.

HMOS (High performance n-channel MOS): LSI, VLSI.

CMOS (Complementary MOS): VLSI, ULSI (Ultra Large Scale Integration).

Better current management combining n- and p-channels.
Originally slower than NMOS.

CMOS-SOS (Silicon On Sapphire).

Low capitance.
100 MHz.

Developed by military for radiation hardness in space and tactical/strategic nuclear warfare environments.

For a long time 0.6 micron geometries were thought to be a limit imposed by the electron microscopes used for mask alignment, but then the X-ray lithography was invented...

1.4 JEDEC (Joint Electronic Device Engeneering Council)

JEDEC was first known for their DIP definitions for memory chips.

JEDEC has suggested a new standard of 3.3 V for all electronic components, including CPUs. CPUs operating at 3.3 V consume less than 50 % of the power of their 5 V equivalents. Intel currently uses a manufacturing process with a resolution of 0.8 micron, but is starting production with a 0.6 micron process. This produces chips that can only operate reliably at 3.3 V, which means that all its future CPUs are likely to operate only at this lower voltage.

1.5 Manufacturers

1.5.1 Intel

The company was founded in 1968 by Gordon Moore, currently the chairman, and the late Bob Noyce. The original name was M & N Electronics, but was changed to Intel (Integrated Electronics).

Intel makes the base models:

i8086/i8088,
i80286,
i80386,
i80486,
Pentium,
i8087,
i80287,
i80387.

iapx stands for Intel Advanced Processor architecture.

Intel lost its claim to the `386' and `486' trademarks, which is why the Pentium is not called the `586'.

Currently, Intel is fighting to protect its various patents and its copyright of the 386 and 486 microcode. The legal situation is complicated by various license agreements made by Intel in the past.

SMM (System Management Mode) can be used to manage the CPU's power demands. When a CPU enters SMM it saves its current state in a special memory area, SMRAM (System Management RAM) and then runs a program, also stored in in SMRAM, the SMM handler. Static core is necessary.
SMM is implemented in all Intel i...SL CPUs. In June 1993, Intel announced it was discontinuing its SL range and instead making all its current processors SL enhanced. Intel has also introduced an Auto Idle state for its clock doubled CPUs: the internal clock can be dropped down to the external clock speed while the processor is waiting for data, returning to full speed as soon as the data arrives.

In February 1994 Intel opened its $750,000,000 costing Fab 10 in Leixlip, Ireland. There the 0.6 micron CMOS Intel i80486DX4 P24C CPU and Intel Pentium CPU series are produced. In the future the Intel P6 CPU and Intel P7 CPU series will be produced here too.
Intel has agreed to invest $7,000,000,000 in Ireland over the next five years.

In June 1994 Intel and Hewlett-Packard agreed to develope a new 64 bit RISC CPU together (Intel P7 CPU / HP PA9000 CPU). The CPU will be based on the HP Precision Architecture (PA) and be able to emulate the Intel X86 architecture.
Together the both companies will invest $1,000,000,000 in the development of the new CPU.

Intel faxback service: 1-800-628-2283.

Intel WWW server: www.intel.com
Intel FTP site: ftp.intel.com

1.5.2 AMD (Advanced Micro Devices)

AMD holds a second source license which dates back to the 8086. In the early days mainframe companies had a rule that no chip would be used in a design, unless it could be bought from at least two companies.

AMD invented a CMOS process that was faster than Intel's and vendors started using them as a primary source.

DEC will manufacture 486 chips for AMD, increasing AMD's production.

In October 1994 AMD Am486 CPUs for AMD in its 0.5 micron technology. The production of AMD Am486DX4 CPUs in Taiwan will start in the third quarter of 1994.

In January 1995 Intel and AMD cancelled all pending lawsuits against eachother. AMD can keep on using the 386 and 486 microcode, but not those of the later CPUs.

AMD European Corporate Applications Technical Hot-Line Support:

euro.tech@amd.com
euro.lit@amd.com

AMD WWW server: www.amd.com
AMD FTP site: ftp.amd.com

1.5.3 IBM (International Bussiness Machines)

Jack Kuehler, Armonk.

IBM's licensing arrangements with Intel preclude them from selling their CPUs directly. They can only sell these FPUs.

From September 1993 IBM is manufacturing the Cyrix 486 CPUs in their 0.5 micron CMOS technology. In the future they will also produce the Cyrix M1 CPU.

IBM WWW server:

1.5.4 Chips & Technologies

George Taylor.
Founded in 1984 by Gordon Campbell.

Chips & Technologies has dropped its development of X86 clones.

1.5.5 Cyrix

Cyrix implemented the chips they wanted to manufacture from the specifications of the originals (clean room). They had Texas Instruments produce these chips for them. A certain number was going to Cyrix to be resold, and the rest was sold by Texas Instruments directly.

From September 1993 IBM is manufacturing the Cyrix 486 CPUs and in the future they will also produce the Cyrix M1 CPU.

Cyrix WWW server: www.cyrix.com

Cyrix fax-bak service: 1-800-46-CYRIX (1-800-462-9749).

1.5.6 Texas Instruments

Texas Instruments used to be Cyrix's major producer (SGS-Thomson was the other one). In 1994 Texas Instruments stopped producing chips for Cyrix and now make their own chips under license from Cyrix. Texas Instruments has rights to make modifications to these chips.

TI FTP site: ftp.ti.com

1.5.7 NexGen

NexGen WWW server: www.nexgen.com

1.5.8 IIT (Integrated Information Technology)

1.5.9 Motorola

George Fisher.

Motorola WWW server: www.mot.com

1.5.10 Apple

Michael Spindler.

Apple WWW server: www.apple.com

1.5.11 HP

HP WWW server: www.hp.com
HP FTP server: ftp.hp.com

1.5.12 DEC (Digital Equipment Corporation)

DEC WWW server: www.dec.com

1.5.13 Renaissance Microsystems Inc.

Gordon Campbell.

Developping PowerPC clones.

1.6 Literature

Andrew S. Tanenbaum: Structured Computer Organization (Prentice-Hall)
A.J. van de Goor: Computer Architecture and Design (Addison-Wesley)
William Stallings: Computer Organization and Architecture (MacMillan)
John L. Hennessy & David A. Patterson: Computer Architecture, a Quantitative Approach (Morgan Kaufman)
Norbert Juffa: Performance Comparison Intel 386DX, Intel RapidCAD, C&T 38600DX, Cyrix 486DLC (USENET News)
Norbert Juffa: Everything you always wanted to know about math coprocessors(USENET News)

CPU Info Center: http://infopad.eecs.berkeley.edu/CIC/

Internet Microcontroller/Microprocessor/CPU Directory: http://www.cera.com/micro.htm

Jaap van Ganswijk: Chip Directory: http://www.xs4all.nl/~ganswijk/chipdir/

Robert Collins: Intel Secrets: undocumented Intel information: http://www.x86.org/

Ken Polsson: Chronology of Events in the History of Microcomputers: http://www.islandnet.com/~kpolsson/comphist.htm

2 CPU (Central Processing Unit)

2.1 Introduction

The central processing unit (CPU) is the "brain" of the computer. Its function is to execute programs stored in the main memory by fetching their instructions, examining them, and then executing them one after another.

2.2 Intel i4004 CPU

4 bit data bus.
12 bit address bus (multiplexed).
Separate address space for instructions and data.

1970.

Package: 16 pin ceramic DIP (Dual In-line Package).

Technology: PMOS.
Die size: 24 mm2.
2250 transistors.

First microprocessor ever build.

2.3 Intel i4040 CPU

Intel i4004 CPU with extra features:

more instructions,
interrupt support.

4 bit data bus.
12 bit address bus (multiplexed).
Separate address space for instructions and data.

1972.

Package: 24 pin ceramic DIP (Dual In-line Package).

Technology: PMOS.

2.4 Intel i8008 CPU

8 bit data bus.
14 bit address bus (multiplexed).

300kHz.

April 1972.

Package: 18 pin ceramic DIP (Dual In-line Package).

Technology: PMOS.
3300 transistors.

2.5 Intel i8080/i8080A CPU

Intel i8008 CPU with stack.

8 bit data bus.
16 bit address bus.

Intel i8080 CPU: 2 MHz, PMOS.
Intel i8080A-2 CPU: 2.67 MHz, NMOS.
Intel i8080A-1 CPU: 3.125 MHz, NMOS.
Intel iM8080A CPU: military (-55 - 125 C).

April 1974.

Package: 40 pin CERDIP (CERamic Dual In-line Package).

Intel i8080 CPU: 1973, PMOS, 4500 transistors.
Intel i8080A CPU: 1976, NMOS, 4000 transistors.

2.6 Zilog Z80 CPU

Intel i8080 CPU upward instruction compatible.

Not Intel i8080 CPU pin compatible.

2.5 MHz: NMOS.
4 MHz: NMOS.
6 MHz: NMOS.
8 MHz: NMOS.
10 MHz: CMOS.

1976.

Package: 40 pin CERDIP (CERamic Dual In-line Package).

2.7 Intel i8085A/i8085AH CPU

Intel i8080 CPU upward instruction compatible.
Extra instructions:

SIM (Set Interrupt Mask),
RIM (Read Interrupt Mask).

Extra interrupt lines, including NMI (Non-Maskable Interrupt).

8 bit data bus.
16 bit address bus.
Data and address bus are multiplexed.

1976.

Intel i8085A CPU: 3 MHz, NMOS.
Intel iM8085A CPU: military (-55 - 125 C), NMOS.
Intel i8085AH-2 CPU: 5 MHz, HMOS.
Intel i8085AH-1 CPU: 6 MHz, HMOS.
Intel iM8085AH CPU: military (-55 - 125 C), HMOS.

Package: 40 pin CERDIP (CERamic Dual In-line Package).

6200 transistors.

2.8 Intel i8086A/i80C86A CPU, Intel i8088A/i80C88A CPU

1 Mbyte address space, 64 kbyte per segment.

Technology: 2.0 micron.
29E3 transistors.

2.8.1 Intel i8086A/i80C86A CPU

16 bit internal data bus.
16 bit external data bus.
20 bit address bus.
Data and address bus are multiplexed.

May 1978.

Intel i8086A CPU: 4 MHz, NMOS.
Intel i8086AH CPU: 5 MHz, HMOS.
Intel i8086AH-2 CPU: 8 MHz, HMOS.
Intel i8086AH-1 CPU: 10 MHz, HMOS.
Intel i80C86A CPU: 5 MHz, CMOS.
Intel i80C86A-2 CPU: 8 MHz, CMOS.
Intel i80C86A-1 CPU: 10 MHz, CMOS.
12 Mhz: CMOS.
Intel iM80C86A CPU: military (-55 - 125 C).

Used in IBM PC clones, IBM PC/XT clones.

Package: 40 pin CERDIP (CERamic Dual In-line Package).

2.8.2 Intel i8088A/i80C88A CPU

16 bit internal data bus.
8 bit external data bus (can co-operate with all Intel i8085 CPU periphery chips).
20 bit address bus.
Data and address bus are multiplexed.

February 1979.

Intel i80C88A CPU: 5 MHz, CMOS.
Intel i80C88A-2 CPU: 8 MHz, CMOS.
Intel i80C88A-1 CPU: 10 MHz, CMOS.
12 MHz: CMOS.

Package: 40 pin CERDIP (CERamic Dual In-line Package).

Used in IBM PC (Personal Computer), IBM PC/XT (eXtended Technology).

2.9 AMD Am8086/Am80C86 CPU, AMD Am8088/Am80C88 CPU

2.9.1 AMD Am8086/Am80C86 CPU

Intel i8086 CPU instruction/pin compatible.

AMD Am8086-1 CPU: 10 MHz, HMOS.
AMD Am80C86 CPU: 5 MHz, CMOS.
AMD Am80C86-2 CPU: 8 MHz, CMOS.
AMD Am80C86-1 CPU: 10 MHz, CMOS.

2.9.2 AMD Am8088/Am80C88 CPU

Intel i8088 CPU instruction/pin compatible.

AMD Am8088 CPU: 5 MHz, HMOS.
AMD Am8088-2 CPU: 8 MHz, HMOS.
AMD Am8088-1 CPU: 10 MHz, HMOS.

2.10 Harris HS80C86/883 CPU, Harris HS80C88/883 CPU

2.10.1 Harris HS80C86/883 CPU

Intel i8086 CPU instruction/pin compatible.

Harris HS80C86/883 CPU: 5 MHz, CMOS.
Harris HS80C86-2/883 CPU: 8 MHz, CMOS.
Harris HS80C86-1/883 CPU: 10 MHz, CMOS.
Harris HSMD80C86 CPU: military (-55 - 125 C), CMOS.

2.10.2 Harris HS80C88/883 CPU

Intel i8088 CPU instruction/pin compatible.

Harris HS80C88/883 CPU: 5 MHz, CMOS.
Harris HS80C88-2/883 CPU: 8 MHz, CMOS.
Harris HS80C88-1/883 CPU: 10 MHz, CMOS.

2.11 Siemens SAB8086 CPU

Intel i8086 CPU instruction/pin compatible.

Siemens SAB8086-2P CPU: 8 MHz.
Siemens SAB8086-1P CPU: 10 MHz.

2.12 Hitachi H80C88 CPU

Intel i8088 CPU instruction/pin compatible.

1982.

Technology: CMOS.

2.13 Contemporary CPUs

Contemporary 16 bit CPUs to 8086/8088 were Zilog Z8000 CPU, Fairchild 9445 CPU, Texas Instruments TI9900 CPU and 8086/8088. Mil-Std 1750A CPU was specified in all contracts of 1979 - 1984 period.
Texas Instruments TI9900 CPU was probably the best of the lot, but Texas Instruments considered it a closed architecture, so no-one used it.

2.14 Intel i80186/i80C186 CPU, Intel i80188/i80C188 CPU

Intel i8086 CPU / Intel i8088 CPU with extra features:

2 programmable DMA controllers (Direct Memory Access),
3 timers,
PIC (Programmable Interrupt Controller),
integrated clock generator,
Intel i80C186 CPU, Intel i80C188 CPU: DRAM refresh control unit,
Intel i80C186 CPU, Intel i80C188 CPU: power save mode,
extra instructions: all of the Intel i80286 CPU real mode instructions.

The Intel i80C188 CPU has no NPX interface.

2.14.1 Intel i80186/i80C186 CPU

16 bit internal data bus.
16 bit external data bus.
20 bit address bus.

1983.

Intel i80186 CPU: 6 MHz, NMOS.
Intel i80186 CPU: 8 MHz, NMOS.
Intel i80186 CPU: 10 MHz, NMOS.
Intel i80C186 CPU: 10 MHz, CMOS.
Intel i80C186-12 CPU: 12.5 MHz, CMOS.
Intel i80C186-16 CPU: 16 MHz, CMOS.
Intel iM80C186 CPU: military (-55 - 125 C), 10 MHz, CMOS.
Intel iM80C186-12 CPU: military (-55 - 125 C), 12.5 MHz, CMOS.

Intel i80C186XL CPU: low power, static core version of the Intel i80C186 CPU:

Intel i80C186XL CPU: 10 MHz, CMOS,
Intel i80C186XL12 CPU: 12.5 MHz, CMOS,
Intel i80C186XL16 CPU: 16 MHz, CMOS,
Intel i80C186XL20 CPU: 20 MHz, CMOS.

Intel i80C186EA CPU: Intel i80C186 CPU with extra features:

idle mode,
power down mode:

Intel i80L186EA8 CPU: 3 V, 8 MHz, CMOS,
Intel i80C186EA12 CPU: 12.5 MHz, CMOS,
Intel i80C186EA16 CPU: 16 MHz, CMOS,
Intel i80C186EA20 CPU: 20 MHz, CMOS.

Intel i80C186EB CPU: low power, static core Intel i80C186 CPU with 2 serial channels, instead of DMA:

Intel i80C186EB-8 CPU: 8 MHz, CMOS,
Intel i80L186EB-8 CPU: 3 V, 8 MHz, CMOS,
Intel i80C186EB-13 CPU: 13 MHz, CMOS,
Intel i80C186EB-16 CPU: 16 MHz, CMOS.

Intel i80C186EC CPU: Intel i80C186EC-13 CPU: 13 MHz, CMOS,

Intel i80C186EC-16 CPU: 16 MHz, CMOS.

2.14.2 Intel i80188/i80C188 CPU

16 bit internal data bus.
8 bit external data bus (can co-operate with all Intel i8085 CPU periphery chips).
20 bit address bus.

1983.

Intel i80188 CPU: 6 MHz, NMOS.
Intel i80188 CPU: 8 MHz, NMOS.
Intel i80C188 CPU: 10 MHz, CMOS.
Intel i80C188-12 CPU: 12.5 MHz, CMOS.
Intel i80C188-16 CPU: 16 MHz, CMOS.

Intel i80C188XL CPU: low power, static core version of the Intel i80C188 CPU:

Intel i80C188XL CPU: 10 MHz, CMOS,
Intel i80C188XL12 CPU: 12 MHz, CMOS,
Intel i80C188XL16 CPU: 16 MHz, CMOS,
Intel i80C188XL20 CPU: 20 MHz, CMOS.

Intel i80C188EA CPU: Intel i80C188 CPU with extra features:

idle mode,
power down mode:

Intel i80L188EA8 CPU: 3 V, 8 MHz, CMOS,
Intel i80C188EA12 CPU: 12.5 MHz, CMOS,
Intel i80C188EA16 CPU: 16 MHz, CMOS,
Intel i80C188EA20 CPU: 20 MHz, CMOS.

Intel i80C188EB CPU: low power, static core Intel i80C188 CPU with 2 serial channels instead of DMA:

Intel i80C188EB-8 CPU: 8 MHz, CMOS,
Intel i80L188EB-8 CPU: 3 V, 8 MHz, CMOS,
Intel i80C188EB-13 CPU: 13 MHz, CMOS,
Intel i80C188EB-16 CPU: 16 MHz, CMOS.

Intel i80C188EC CPU: Intel i80C188 CPU with extra features:

low power,
static core,
2 serial channels,
4 DMA channels,
32 bit watchdog timer:

Intel i80C188EC-13 CPU: 13 MHz, CMOS,
Intel i80C188EC-16 CPU: 16 MHz, CMOS.

2.15 AMD Am80186/Am80188 CPU

Intel i80186/i80188 CPU upward instruction compatible.

2.15.1 AMD Am80L186 CPU

Intel i80186 CPU bus interface.

16 MHz: 3.3 V, 1995.

AMD Embedded Processors E86 Family.

2.15.2 AMD Am80L188 CPU

Intel i80188 CPU bus interface.

16 MHz: 3.3 V, 1995.

AMD Embedded Processors E86 Family.

2.15.3 AMD Am186EM CPU

Intel i80286 CPU style bus interface.
Extra Features:

2 DMA channels,
watchdog timer,
asynchronous & synchronous serial ports,
32 programmable I/O pins.

25 MHz: 1995.
33 MHz: 1995.
40 MHz: 1995.

Package: PQT100.

AMD Embedded Processors E86 Family.

2.16 NEC V30/V20 CPU

Intel i80186 CPU / Intel i80188 CPU upward instruction compatible.
No protected mode.
Extra features:

extra instructions: BCD,
Intel i8080 CPU simulation,
fewer CPI (Cycles Per Instruction).

2.16.1 NEC V30 CPU

Intel i8086 CPU pin compatible.

10 MHz.

mPD70116.

NEC V30H CPU:

10, 12, 16 MHz,
packages:
- 40 pin DIP (Dual In-line Package),
- 44 pin PLCC (Plastic Leaded Chip Carrier),
- 52 pin PFP (QFP (Quad Flat Package)),
mPD70116H.

NEC V35 CPU:

extra instructions for register bank switches and task switches,
packages:
- 84 pin PLCC (Plastic Leaded Chip Carrier),
- 94 pin QFP (Quad Flat Package),
mPD70330, mPD70332.

NEC V35 Plus CPU:

NEC V35 CPU with integrated peripherals:
- PIC,
- DMA,
- ports,
- serial,
- timer,
256 bytes RAM,
8 kbyte ROM,
mPD70335.

NEC V35 Software Guard CPU:

NEC V35 CPU with 8086 emulation mode and security mode,
mPD70337.

NEC V50 CPU:

undefined opcode triggers INT6,
same speeds,
packages:
- 68 pin PGA (Pin Grid Array),
- 68 pin PLCC (Plastic Leaded Chip Carrier),
- 80 pin PFP (QFP (Quad Flat Package)),
mPD70216.

NEC V50H CPU:

10, 12, 16 MHz,
packages:
- 68 pin PGA (Pin Grid Array),
- 80 pin PFP (QFP (Quad Flat Package)).
mPD70216H.

NEC V55 CPU:

NEC V50 CPU,
speeds up to 16 MHz.

2.16.2 NEC V20 CPU

Intel i8088 CPU pin compatible.

8 MHz.
10 MHz.

mPD70108

Also made by Sony under license from NEC V20H CPU:

10, 12, 16 MHz,
packages:
- 40 pin DIP (Dual In-line Package),
- 44 pin PLCC (Plastic Leaded Chip Carrier),
- 52 pin PFP (QFP (Quad Flat Package)),
mPD70108H.

NEC V25 CPU:

extra instructions for register bank switches and task switches,
packages:
- 84 pin PLCC (Plastic Leaded Chip Carrier),
- 94 pin QFP (Quad Flat Package),
mPD70320, mPD70322.

NEC V25 Plus CPU:

NEC V25 CPU with integrated peripherals:
- PIC,
- DMA,
- ports,
- serial,
- timer,
256 bytes RAM,
8 kbyte ROM,
mPD70325.

NEC V25 Software Guard CPU:

NEC V25 CPU with 8086 emulation mode and security mode,
mPD70327.

NEC V40 CPU:

undefined opcode triggers INT6,
same speeds,
packages:
- 68 pin PGA (Pin Grid Array),
- 68 pin PLCC (Plastic Leaded Chip Carrier),
- 80 pin PFP (QFP (Quad Flat Package)),
mPD70208.

NEC V40H CPU:

10, 12, 16 MHz,
packages:
- 68 pin PGA (Pin Grid Array),
- 80 pin PFP (QFP (Quad Flat Package)),
mPD70208H.

NEC V45 CPU:

NEC V40 CPU,
speeds up to 16 MHz.

2.17 Siemens SAB80186 CPU, Siemens SAB80188 CPU

2.17.1 Siemens SAB80186 CPU

Intel i80186 CPU instruction/pin compatible.

Siemens SAB80186-N CPU: 8 MHz.
Siemens SAB80186-1 CPU: 10 MHz.
Siemens SAB80186-16 CPU: 16 MHz.

2.17.2 Siemens SAB80188 CPU

Siemens SAB80188-N CPU: 8 MHz.
Siemens SAB80188-1N CPU: 10 MHz.

2.18 Intel i80886 CPU

2.19 Intel i80286 CPU

Real mode: Intel i8086/i8088 CPU mode.
Protected mode:

16 MByte address space,
64 kbyte per segment,
1 Gbyte virtual memory.

16 bit data bus.
24 bit address bus.

1983.

6 MHz.
8 MHz: PLCC (Plastic Leaded Chip Carrier).
10 MHz: PLCC (Plastic Leaded Chip Carrier).
12 MHz: PLCC (Plastic Leaded Chip Carrier).
16 MHz: PLCC (Plastic Leaded Chip Carrier).
20 MHz.

Package: 68 pin CERDIP (CERamic Dual In-line Package).

Used in IBM PC/AT (Advanced Technology).

Technology: HMOS.
134E3 transistors.

2.20 AMD Am80286/Am80C286 CPU

Intel i80286 CPU instruction/pin compatible.

AMD Am80286 CPU: 8 MHz, HMOS.
AMD Am80286 CPU: 10 MHz, HMOS.
AMD Am80286 CPU: 12 MHz, HMOS.
AMD Am80286 CPU: 16 MHz, HMOS.
AMD Am80C286 CPU: 10 MHz, CMOS.
AMD Am80C286 CPU: 12 MHz, CMOS.
AMD Am80C286 CPU: 16 MHz, CMOS.
AMD Am80C286 CPU: 20 MHz, CMOS.
AMD Am80EC286 CPU: low power version of the 2.21 Harris 80C286 CPU

Intel i80286 CPU instruction/pin compatible.

10 MHz.
12.5 MHz.
16 MHz.
20 MHz.
25 MHz.

Technology: CMOS.

2.22 Siemens SAB80286 CPU

Intel i80286 CPU instruction/pin compatible.

Siemens SAB80286 CPU: 8 MHz.
Siemens SAB80286-1-N CPU: 10 MHz.
Siemens SAB80286-12-N CPU: 12 MHz.
Siemens SAB80286-16 CPU: 16 MHz.

2.23 Intel i80386 CPU

Real mode: Intel i8086/i8088 CPU mode.
Protected mode:

64 Tbyte virtual memory,
4 Gbyte per segment.

Virtual 8086 mode (V86 mode): parallel simulation of more virtual Intel i8086/i8088 CPUs.

POPAD bug: EAX register is trashed when there is a memory access instruction directly after the POPAD instruction.

2.23.1 Intel i80386/i80386DX CPU

32 bit internal data bus.
32 bit external data bus (DX: Double-word eXternal).
32 bit address bus.

12 MHz: first 16 MHz CPUs had clock speed troubles and were released as 12 MHz items.
16 MHz: early Intel i80386 CPUs had a bug in the 32 bit MUL instruction (MUL bug); it is fixed in the double-sigma step level, no longer available.
20 MHz: no longer available.
25 MHz: iCOMP 49.
33 MHz: 2000 mW, iCOMP 68.

October 1985.

Package: 132 pin PGA (Pin Grid Array).

Technology: 0.8 micron CMOS.
275E3 transistors.

ID: AH=0x03 (Intel i80386 CPU).

ID:

step level A (Intel i80386 CPU): DH = 0x00 (model ID, family ID),
step level B0-B10 (Intel i80386 CPU, CMOS III): DH = 0x03 (model ID, family ID), DL = 0x03 (revision),
step level D0 (Intel i80386DX CPU, CMOS III): DH = 0x03 (model ID, family ID), DL = 0x05 (revision),
step level D1-D2 (Intel i80386DX CPU, CMOS IV): DH = 0x03 (model ID, family ID), DL = 0x08 (revision),
step level Ex, Fx: DH = 0x03 (model ID, family ID), DL = 0x08 (revision).

2.23.2 Intel i80386SX CPU

32 bit internal data bus.
16 bit external data bus (SX: Single-word eXternal).
24 bit address bus.

June 1988.

16 MHz.
20 MHz: iCOMP 32.
25 MHz: iCOMP 39.
33 MHz.

Package: 100 pin QFP (Quad Flat Package).

Technology: 0.8 micron CMOS.

ID:

step level A0: DH = 0x23 (model ID, family ID), DL = 0x04 (revision),
step level B: DH = 0x23 (model ID, family ID), DL = 0x05 (revision),
step level C, D, E: DH = 0x23 (model ID, family ID), DL = 0x08 (revision).

2.23.3 Intel i80386SL CPU

Low power version of the Intel i80386SX CPU: SMM (System Management Mode).
Static core.
Extra pins assigned for power management.

Extra features:

PI-bus (Peripheral Interface),
cache controller, tag RAM,
MCU (Memory Control Unit),
ISA-bus driver (Industry Standard Architecture).

Intel i80386SX CPU upward pin compatible.
Other package: 196 pin surface mounted QFP (Quad Flat Package) (KC80386SLB1A, ISA SX621).

October 1990.

16 MHz.
20 MHz.
25 MHz, iCOMP 41.
33 MHz.

Technology: CMOS.

ID:

step level A0: DH = 0x43 (model ID, family ID), DL = 0x10 (revision),
step level A1: DH = 0x43 (model ID, family ID), DL = 0x10 (revision),
step level A2: DH = 0x43 (model ID, family ID), DL = 0x10 (revision),
step level A3: DH = 0x43 (model ID, family ID), DL = 0x10 (revision),
step level B0: DH = 0x43 (model ID, family ID), DL = 0x11 (revision),
step level B1: DH = 0x43 (model ID, family ID), DL = 0x11 (revision).

Signature register (0x30E, OMCU):

step level A0: 0x4300,
step level A1: 0x4300,
step level A2: 0x4301,
step level A3: 0x4302,
step level B0: 0x4310,
step level B1: 0x4311.

2.23.4 Intel RapidCAD CPU

Intel i80386 CPU with FPU (Floating Point Unit) (same implementation as Intel i80486DX CPU).

The Intel RapidCAD CPU consists of a set of 2 chips. The Intel RapidCAD-1 (132 pin PGA) contains the Intel i80386 CPU with FPU. The Intel RapidCAD-2 (68 pin PGA) fits in the Intel i80387DX NPX socket and contains a PLA for the FERR signal generation.

Intel i80386DX CPU / Intel i80387DX NPX pin compatible.

1992.

25 MHz.
33 MHz: 2.6 W typical, 3500 mW max.

800.000 transistors.
Technology: 0.8 micron CHMOS IV.

ID:

step level A: DH = 0x03 (family ID), DL = 0x40 (model ID, revision),
step level B: DH = 0x03 (family ID), DL = 0x41 (model ID, revision).

2.23.5 Intel i80376 microprocessor

Embedded version of Intel i80386SX CPU.
Intel i80386SX CPU pin compatible.

Intel i80386 CPU instruction set, 32 bit protected mode only, no real mode, no V86 mode, no 286 mode.
No MMU (Memory Management Unit).

16 MHz.
20 MHz.

1988.

Package:

100 pin QFP (Quad Flat Package),
88 pin PGA (Pin Grid Array).

ID:

step level A0: DH = 0x33 (model ID, family ID), DL = 0x05 (revision),
step level B: DH = 0x33 (model ID, family ID), DL = 0x08 (revision).

2.23.6 Intel i386SX microprocessor

Embedded version of Intel i80386SX CPU.
Static core.

24 bit address bus.

16 MHz: 5 V, 0-16 MHz, 1993.
20 MHz: 5 V, 0-20 MHz, 1993.
25 MHz: 5 V, 0-25 MHz, 1993.

Package:

100 pin PQFP (Plastic Quad Flat Package),
die,
military (-55 - 125 C).

Technology: CMOS.

ID: DH = 0x23 (model ID, family ID), DL = 0x09 (revision).

2.23.7 Intel i386CX microprocessor

Embedded version of Intel i80386SX CPU.
Static core.

SMM (System Management Mode): system & power management:

idle mode,
powerdown,
powersave.

26 bit address bus.

12 MHz: 3 V, 0-12 MHz, 1993.
20 MHz: 3.3 V, 0-20 MHz, 1993.
25 MHz: 5 V, 0-25 MHz, 1993.

Package:

100 pin PQFP (Plastic Quad Flat Package),
100 pin SQFP (Shrink Quad Flat Package),
die,
military (-55 - 125 C).

Technology: CMOS.

ID: step level A: DH = 0x23 (model ID, family ID), DL = 0x09 (revision).

2.23.8 Intel i386EX microprocessor

Embedded version of Intel i80386SX CPU.
Static core.

SMM (System Management Mode): system & power management:

idle mode,
powerdown,
powersave.

26 bit address bus.

16 MHz: 3 V, 0-16 MHz, 1994.
20 MHz: 3.3 V, 0-20 MHz, 1994.
25 MHz: 5 V, 0-25 MHz, 1994.

Package:

132 pin PQFP (Plastic Quad Flat Package),
144 pin SQFP (Shrink Quad Flat Package),
die,
military (-55 - 125 C).

Technology: CMOS.

ID: step level A: DH = 0x23 (model ID, family ID), DL = 0x09 (revision).

2.24 AMD Am386 CPU

Intel i80386 CPU instruction compatible.
Same core and microcode as Intel i80386 CPU.

2.24.1 AMD Am386DX CPU

Low power.

Intel i80386DX CPU instruction/pin compatible.
Intel i80386DX IV CPU microcode.

March 1991.

16 MHz: 2-16 MHz.
20 MHz: 2-20 MHz.
25 MHz: 2-25 MHz.
33 MHz: 2-33 Mhz.
40 MHz: 2-40 MHz.

Technology: 0.8 micron CMOS.

ID:

step level A: DH = 0x03 (model ID, family ID), DL = 0x05 (revision),
step level B: DH = 0x03 (model ID, family ID), DL = 0x08 (revision).

2.24.2 AMD Am386DXL CPU

Low power version of AMD Am386DX CPU.
Static core.
Intel i80386DX IV CPU microcode.

Intel i80386DX CPU upward pin compatible.

March 1991.

20 MHz.
25 MHz.
33 MHz.
40 MHz.

Technology: CMOS.

ID:

step level A: DH = 0x03 (model ID, family ID), DL = 0x05 (revision),
step level B: DH = 0x03 (model ID, family ID), DL = 0x08 (revision).

2.24.3 AMD Am386DXLV CPU

Low power (SMM: System Management Mode), low voltage (3.3 V - 4.5 V) version of AMD Am386DX CPU.
Static core.

Intel i80386DX CPU upward pin compatible.

October 1991.

25 MHz.
33 MHz.

Technology: CMOS.

2.24.4 AMD Am386SX CPU

Low power.
Extra pins assigned for power management.

Intel i80386SX CPU upward pin compatible.

July 1991.

16 MHz: 2-16 MHz.
20 MHz: 2-20 MHz.
25 MHz: 2-25 MHz, no longer available.
33 MHz: 2-33 MHz.
40 MHz: 2-40 MHz.

Technology: 0.8 micron CMOS.

ID:

step level A1: DH = 0x23 (model ID, family ID), DL = 0x05 (revision),
step level B: DH = 0x23 (model ID, family ID), DL = 0x08 (revision).

2.24.5 AMD Am386SXL CPU

Low power version of AMD Am386SX CPU.
Static core.

July 1991.

20 MHz: 0-20 MHz.
25 MHz: 0-25 MHz.
33 MHz: 0-33 MHz.
40 MHz: 0-40 MHz.

Technology: CMOS.

ID:

step level A1: DH = 0x23 (model ID, family ID), DL = 0x05 (revision),
step level B: DH = 0x23 (model ID, family ID), DL = 0x08 (revision).

2.24.6 AMD Am386SXLV CPU

Low power (SMM: System Management Mode), low voltage (3.3 V - 4.5 V) version of AMD Am386SX CPU.
Static core.

October 1991.

20 MHz.
25 MHz.
33 MHz.

Technology: CMOS.

2.24.7 AMD Am386DE CPU

Embedded static version of the AMD Am386DX CPU.

25 MHz: 1995.
33 MHz: 1995.

Package: PQB132.

AMD Embedded Processors E86 Family.

2.24.8 AMD Am386SE CPU

Embedded static version of the AMD Am386SX CPU.

25 MHz: 1995.
33 MHz: 1995.

Package: PQB100.

AMD Embedded Processors E86 Family.

2.24.9 AMD Am386EM CPU

Intel i80386 CPU instruction compatible.
Extra features:

4 DMA channels with flyby and chaining support,
watchdog timer,
asynchronous & synchronous serial ports,
32 progrmmable I/O pins,
DRAM controller,
96 Mbyte address space,
JTAG support.

25 MHz: 1995.
33 MHz: 1995.
40 MHz: 1995.

Package: PQR132.

AMD Embedded Processors E86 Family.

2.25 IBM 386 CPU

Intel i80386 CPU instruction compatible.
Some instructions are executed faster than when executed by the Intel i80386 CPU.

2.25.1 IBM 386SLC CPU

Low power.
Extra pins assigned for power management.

8 kbyte cache.
To be enabled via software.

October 1991.

16 MHz.
20 MHz.
25 MHz: 2.5 W.

Intel i80386SX CPU upward pin compatible (100 pin MQFP).

Technology: CMOS.
Die size: 161 mm2.

ID: step level A: DH = 0xA3 (model ID, family ID), DL = 0xXX (revision).

2.26 Chips & Technologies 386 CPU

Intel i80386 CPU instruction compatible, including undocumented LOADALL386 instruction.
Own microcode (clean room).
Some instructions are executed faster than when executed by the Intel i80386 CPU.

2.26.1 Chips & Technologies Super386 38600DX CPU

Co-operation with an appropriate NPX causes communication problems, which causes the over-all performance to drop below that of an Intel i80386DX CPU with NPX.

Intel i80386DX CPU pin compatible.

33 MHz.
40 MHz: 1650 mW.

No longer available.

Technology: CMOS.

2.26.2 Chips & Technologies 38605DX CPU

512 byte instruction cache.

32 bit internal data bus.
32 bit external data bus.
32 bit address bus.
Not Intel i80386DX CPU pin compatible.

No longer available.

Package: 144 pin PGA (Pin Grid Array).

Technology: CMOS.

2.26.3 Chips & Technologies 38600SX CPU

Intel i80386SX CPU pin compatible.

Never released.

Technology: CMOS.

2.27 IBM 386/486 hybrid CPU

Intel i80486 CPU instruction compatible, no FPU (Floating Point Unit).
Intel i80386 CPU bus interface.

2.27.1 IBM 486DLC CPU

Intel i80386 CPU core, enhanced by IBM.

16 kbyte cache: 4-way set associative, write through.
To be enabled via software (BIOS).

32 bit internal data bus.
32 bit external data bus.
32 bit address bus.
Not Intel i80386DX CPU pin compatible.

Technology: CMOS.

2.27.2 IBM 486DLC2 CPU

Clock doubled version of the IBM 486DLC CPU.

Intel i80386 CPU core, enhanced by IBM.

16 kbyte cache: 4-way set associative, write through.
To be enabled via software (BIOS).

Intel i80386DX CPU pin compatible.

November 1993.

33/66 MHz.

Technology: CMOS.

2.27.3 IBM 486SLC CPU

Intel i80386 CPU core, enhanced by IBM.

16 kbyte cache: 4-way set associative, write through.
To be enabled via software (BIOS).

32 bit internal data bus.
16 bit external data bus.
24 bit address bus.
Not Intel i80386SX CPU pin compatible.

16 MHz.
20 MHz.
20 MHz: 3.3 V, 1.0 W.
25 MHz.
25 MHz: 3.3 V, 1.3 W.

Technology: CMOS.

ID: step level A: DH = 0xA4 (model ID, family ID), DL = 0xXX (revision).

2.27.4 IBM 486SLC2 CPU

Clock doubled version of the IBM 486SLC CPU.
Low voltage: 3.3 V.

Intel i80386 CPU core, enhanced by IBM.

16 kbyte cache: 4-way set associative, write through, 16 byte line size.
To be enabled via software (BIOS).

Intel i80386SX CPU pin compatible (100 pin MQFP).

December 1992.

16/32 MHz.
20/40 MHz: 1.7 W.
25/50 MHz: 1993, 2.3 W.
33/66 MHz: 1993.
40/80 MHz: 1993.

1.349E6 transistors.
Die size: 69 mm2.

ID:

step level Ax: DH = 0xA4 (model ID, family ID), DL = 0x1X (revision),
step level Bx: DH = 0xA4 (model ID, family ID), DL = 0x2X (revision).

2.27.5 IBM 486BLX CPU (Blue Lightning)

Intel i80486 CPU core and microcode, no FPU.

16 kbyte cache: 4-way set associative, write through, 16 byte line size.
To be enabled via software (BIOS).

Low power (3.3 V).
Power management: SMM (System Management Mode).
Static core.

15 MHz.
20 Mhz.
25 MHz.
33 MHz.

Intel i80386DX CPU upward pin compatible / AMD Am386DXL/Am386DXLV CPU pin compatible (132 pin MQFP).

Technology: 0.8 micron CMOS.
Die size: 82 mm2.
1.4E6 transistors.

2.27.6 IBM 486BLX2 CPU (Blue Lightning)

Clock doubled version of the IBM 486BLX CPU.

15/30 MHz.
20/40 MHz.
25/50 MHz: 1993.
33/66 MHz: 1993.

2.27.7 IBM 486BLX3 CPU (Blue Lightning)

Clock tripled version of the IBM 486BLX CPU.

15/45 MHz.
20/60 MHz.
25/75 MHz: 1993.
33/99 MHz: 1993.

ID: step level A: DH = 0x84 (model ID, family ID), DL = 0xXX (revision).

2.28 Cyrix 386/486 hybrid CPU

Intel i80486 CPU instruction compatible, no FPU (Floating Point Unit).
Own core (clean room): not 100% compatible.
Intel i80386 CPU bus interface.

2.28.1 Cyrix Cx486DLC CPU

First generation 40 MHz CPUs had a bug: using a NPX (Cyrix Fasmath EMC87 NPX, Cyrix FasMath Cx83D87 NPX (until November 1991), IIT IIT-3C87 NPX) caused crashes. These are caused by synchronisation errors in FSAVE and FSTOR instructions. Later, improved CPUs have an AB prefix printed in the lower right corner. The Cyrix FasMath Cx387+ NPX (European name for Cyrix FasMath Cx83D87 NPX from November 1991) causes no trouble when co-operating with a bad Cyrix Cx486DLC CPU.

Static core.

1 kbyte unified cache:

write through,
direct mapped / 2-way set associative,
maximum of 4 non-cachable areas.

Hit rate:

65% without support of cache by motherboard, because of flush at DMA,
85% with support of cache by motherboard (Cache Coherency Support).

To be enabled via software (BIOS).

Intel i80386DX CPU upward pin compatible.

June 1992.

25 MHz.
33 MHz.
40 MHz: 2800 mW.

Clock Skewing Correction Circuit.

Contains a fast extra 16x16 bit multiplier.

Extra pins assigned for cache, power and A20 management:

cache management: KEN#, FLUSH#, RPLSET#, RPLVAL#,
power management: SUSP#, SUSPA#,
A20 management: A20M#.

Technology: CMOS.

DIR0 register: 0x01.

2.28.2 Cyrix Cx486SLC CPU

Static core.

1 kbyte unified cache:

write through / write back,
direct mapped / 2-way set associative,
maximum of 4 non-cachable areas.

hit rate:

65% without support of cache by motherboard, because of flush at DMA,
85% with support of cache by motherboard (Cache Coherency Support).

To be enabled via software (BIOS).

Intel i80386SX CPU upward pin compatible.

March 1992.

20 MHz.
25 MHz.
33 MHz.
40 MHz.

Clock Skewing Correction Circuit.

Contains a fast extra 16x16 bit multiplier.

Extra pins assigned for cache, power and A20 management:

cache management: KEN#, FLUSH#, RPLSET#, RPLVAL#,
power management: SUSP#, SUSPA#,
A20 management: A20M#.

Technology: CMOS.

ID:

step level A: DH = 0x04 (family ID), DL = 0x1X (revision),
DH = 0x04 (family ID), DL = 0x2X (revision).

No DIR0 register.

2.28.3 Cyrix Cx486SLC/e CPU

Low power (SMM: System Management Mode) version of Cyrix Cx486SLC CPU.
Static core.

December 1992.

25 MHz.
33 MHz.

Technology: CMOS.

DIR0 register: 0x00.

2.28.4 Cyrix Cx486SLC/e-V CPU

Low power (SMM: System Management Mode), low voltage (3.3 V) version of Cyrix Cx486SLC CPU.
Static core.

December 1992.

20 MHz.
25 MHz.

Technology: CMOS.

DIR0 register: 0x00.

2.28.5 Cyrix Cx486DLC / Cx486SLC CPU incompatibilities

Same registers.
Same instruction set.
Differences in execution time of various instructions, average CPI (Cycles Per Instruction) about equal.

Crashes with:

NextStep,
DBOS 1.0 DOS extender of Salford FTN/386,
Fortran compiler.

2.28.6 Cyrix Cx486DLC2 CPU

Clock doubled version of the Cyrix Cx486DLC CPU.

Power Management: SMM (System Management Mode).
Static core.

DIR0 register: 0x03.

2.28.7 Cyrix Cx486SLC2 CPU

Clock doubled version of the Cyrix Cx486SLC CPU

Power Management: SMM (System Management Mode).
Static core.

November 1993.

25/50 MHz.

Technology: CMOS.

DIR0 register: 0x02.

2.28.8 Cyrix Cx486DRx CPU

DIR0 register: 0x05.

2.28.9 Cyrix Cx486SRx CPU

Intel i80486 CPU instruction compatible, no FPU (Floating Point Unit).

The chip is placed over the surface mounted 80386SX CPU. The original CPU is disabled by using the FLOAT pin. Older 16 MHz 80386SX CPUs can not be upgraded (Cyrix can supply a compatibility test program).

1 kbyte cache.

DIR0 register: 0x04.

2.28.10 Cyrix Cx486DRx2 CPU

Clock doubled version of the Cyrix Cx486DRx CPU.

Incompatibilities:

AT&T / Olivetti 386DX-16 and 386DX-20 systems,
Sun i386 systems,
Memorex 386 systems,
IBM PS/2 Model 70/16 MHz (85 ns memory required),
early Compaq Deskpro 386/16 MHz systems with 287 NPX (NPX to be removed).

September 1993.

16/32 MHz.
20/40 MHz: heat sink.
25/50 MHz: heat sink.
33/66 MHz.

Technology: CMOS.

DIR0 register: 0x07.

2.28.11 Cyrix Cx486SRx2 CPU

Clock doubled version of the Cyrix Cx486SRx CPU.

December 1993.

16/32 MHz.
20/40 MHz.
25/50 MHz.

Technology: CMOS.

DIR0 register: 0x06.

2.28.12 Cyrix Cx486DRu CPU

Direct Replacement Unit.
In fact a Cyrix Cx486DLC CPU with some additional hardware on a little PCB that fits in a PGA (Pin Grid Array).

DIR0 register: 0x09.

2.28.13 Cyrix Cx486SRu CPU

DIR0 register: 0x08.

2.28.14 Cyrix Cx486DRu2 CPU

Clock doubled version of the Cyrix Cx486DRu CPU.

16/32 MHz.
20/40 MHz.
25/50 MHz.

DIR0 register: 0x0B.

2.28.15 Cyrix Cx486SRu2 CPU

Clock doubled version of the Cyrix Cx486SRu CPU.

DIR0 register: 0x0A.

2.29 Texas Instruments 386/486 hybrid CPU

2.29.1 Texas Instruments TI486DLC CPU

Cyrix Cx486DLC CPU.

ID:

step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

2.29.2 Texas Instruments TI486SLC CPU

Cyrix Cx486SLC CPU.

ID:

step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

2.29.3 Texas Instruments TI486SXL-S-GA CPU (Potomac)

Intel i80486 CPU instruction compatible, no FPU (Floating Point Unit).
Intel i80386DX CPU bus interface.

8 kbyte cache: write through, 2-way set associative, 1024 sets, 4 bytes per line.

40 MHz: february 1994.

Package: ceramic PGA (Pin Grid Array).

Technology: CMOS.

ID:

step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.

2.29.4 Texas Instruments TI486SXL-VS-GA CPU (Potomac)

Low power (3.3 V) version of the Texas Instruments TI486SXL-S-GA CPU.

33 MHz: february 1994.

Technology: CMOS.

ID:

step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.

2.29.5 Texas Instruments TI486SXL2-S-GA CPU (Potomac)

Clock doubled version of the Texas Instruments TI486SXL-S-GA CPU.

20/40 MHz: february 1994.
25/50 MHz: february 1994.

Technology: CMOS.

ID:

step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.

2.29.6 Texas Instruments TI486SXL2-VS-GA CPU (Potomac)

Clock doubled, low power (3.3 V) version of the Texas Instruments TI486SXL-S-GA CPU.

20/40 MHz: february 1994.

Technology: CMOS.

ID:

step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.

2.29.7 Texas Instruments TI486SXLC-PAF CPU (Potomac)

Intel i80486 CPU instruction compatible, no FPU (Floating Point Unit).
Intel i80386SX CPU bus interface.

8 kbyte cache: write through, 2-way set associative, 1024 sets, 4 bytes per line.

33 MHz: february 1994.

Package: QFP (Quad Flat Package).

Technology: CMOS.

ID:

step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.

2.29.8 Texas Instruments TI486SXLC-V-PAF CPU (Potomac)

Low power (3.3 V) version of the Texas Instruments TI486SXLC-PAF CPU.

25 MHz: february 1994.
33 MHz: february 1994.

Technology: CMOS.

ID:

step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.

2.29.9 Texas Instruments TI486SXLC2-PAF CPU (Potomac)

Clock doubled version of the Texas Instruments TI486SXLC-PAF CPU.

20/40 MHz: february 1994.
25/50 MHz: february 1994.

Technology: CMOS.

ID:

step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.

2.29.10 Texas Instruments TI486SXLC2-V-PAF CPU (Potomac)

Clock doubled, low power (3.3 V) version of the Texas Instruments TI486SXLC-PAF CPU.

20/40 MHz: february 1994.

Technology: CMOS.

ID:

step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.

2.29.11 Texas Instruments announcements

Rio Grande series: Potomac series follow-up.

2.30 Intel i80486 CPU

Intel i80386 CPU upward instruction compatible.
Extra instructions.

8 kbyte unified cache: write through, 4-way set associative, 128 sets, 16 bytes per cache line, 4 write buffers, only invalidation of a complete cache line, 96 % hit rate.

32 bit internal data bus.
32 bit external data bus.
32 bit address bus.

Execution unit:

5-stage pipeline,
barrel shifter,
branch taken / not taken prediction (BTB: Branch Target Buffer).

Burst mode memory access:

first access: 2 clock cycles,
every next access: 1 clock cycle.

CPUID: "GenuineIntel".

2.30.1 Intel i80486DX CPU

Build-in FPU (Floating Point Unit).

April 1989.

20 MHz: CMOS.
25 MHz: 2600 mW, CHMOS IV, iCOMP 122, no longer available.
33 MHz: 3500 mW, CHMOS IV.
50 MHz: June 1991, 3875 mW, CHMOS V.

Upgrading:

Intel i80486DX2 CPU (ODPR)

Intel Overdrive CPU (ODP: Intel i80486DX2 CPU)

Intel i80486DX4 CPU (ODPR)

Intel Overdrive CPU (ODP: Intel i80486DX4 CPU)

Intel Overdrive CPU (ODP: Intel Pentium CPU)

Package: 168 pin PGA (Pin Grid Array).

1.2E6 transistors.

From June 1993 (Intel i80486DX-S CPU):

SL Enhanced.

33 MHz: iCOMP 166.
50 MHz: iCOMP 249.

CPUID: family=0x4, model=0x1.

From June 1993:

SL Enhanced.
Low power: 3.3 V.

33 MHz.

No longer available from second quarter 1995.

ID (25 - 33 MHz, CMOS IV):

step level A0, A1: DH = 0x04 (family ID), DL = 0x00 (model ID, revision),
step level B2-B6: DH = 0x04 (family ID), DL = 0x01 (model ID, revision),
step level C0: DH = 0x04 (family ID), DL = 0x02 (model ID, revision),
step level C1: DH = 0x04 (family ID), DL = 0x03 (model ID, revision),
step level D0: DH = 0x04 (family ID), DL = 0x04 (model ID, revision).

ID (50 MHz, CMOS IV):

step level cA2, cA3: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level cB0, cB1: DH = 0x04 (family ID), DL = 0x11 (model ID, revision),
step level cC0: DH = 0x04 (family ID), DL = 0x13 (model ID, revision),
step level aA0, aA1 (SL Enhanced): DH = 0x04 (family ID), DL = 0x14 (model ID, revision),
step level aB0 (SL Enhanced): DH = 0x04 (family ID), DL = 0x15 (model ID, revision).

2.30.2 Intel i80486SL CPU

Intel i80486DX CPU with extra features:

DRAM controller,
ISA ,(Industry Standard Architecture) controller,
local PI-bus controller (Peripheral Interconnect),
power management: SMM (System Management Mode).

Static core.

25 Mhz.
33 MHz.

Not Intel i80486DX CPU pin compatible.
196 pin PQFP (Plastic Quad Flat Package).

Technology: CMOS.

From June 1993 replaced by Intel i80486DX-S CPU.

ID: step level A: DH = 0x04 (family ID), DL = 0x40 (model ID, revision).

2.30.3 Intel i80486DXL CPU

Intel i80486DX CPU with extra features:

SMM (System Management Mode),
stop clock,
power saving features.

Static core.

Technology: CMOS.

2.30.4 Intel i80486SX CPU

No build-in FPU (Floating Point Unit):

Intel i80486DX CPU die with FPU disabled,
currently FPU not implemented (resulting in a smaller chip, plastic package).

One extra pin assigned to allow an Intel i80487SX NPX to disable this CPU.
Not Intel i80486DX CPU upward pin compatible.
Package: 168 pin PGA (Pin Grid Array).

April 1991.

16 MHz: 1991, no longer available.
20 MHz: 1991, iCOMP 78, no longer available.
25 MHz: 1991.
33 MHz: 1991.

Upgrading:

Intel i80486DX CPU (ODPR: Intel i80486DX CPU with Intel i80486SX CPU pin layout),
Intel i80486DX2 CPU (ODPR: Intel i80486DX2 CPU with Intel i80486SX CPU pin layout),
Intel Overdrive CPU (ODP: Intel i80486DX2 CPU),
Intel i80486DX4 CPU (ODPR: Intel i80486DX4 CPU with Intel i80486SX CPU pin layout),
Intel Overdrive CPU (ODP: Intel i80486DX4 CPU),
Intel Overdrive CPU (ODPR: Intel Pentium CPU with Intel i80486SX CPU bus interface),
Intel Overdrive CPU (ODP: Intel Pentium CPU).

Package:

168 pin PGA (Pin Grid Array),
208 pin PQFP (Plastic Quad Flat Package).

Technology: CMOS.

From June 1993 (Intel i80486SX-S CPU):

SL Enhanced.

25 MHz: iCOMP 100 (by define).
33 MHz: iCOMP 136.

CPUID: family=0x4, model=0x2.

From June 1993:

SL Enhanced.
Low Power: 3.3 V.

25 MHz.
33 MHz.

ID:

step level A0: DH = 0x04 (family ID), DL = 0x20 (model ID, revision),
step level B0: DH = 0x04 (family ID), DL = 0x22 (model ID, revision),
step level cA0: DH = 0x04 (family ID), DL = 0x27 (model ID, revision),
step level cB0: DH = 0x04 (family ID), DL = 0x28 (model ID, revision),
step level D: DH = 0x04 (family ID), DL = 0x23 (model ID, revision),
step level E: DH = 0x04 (family ID), DL = 0x2A (model ID, revision),
step level gAx: DH = 0x04 (family ID), DL = 0x24 (model ID, revision),
step level aA0, aA1: DH = 0x04 (family ID), DL = 0x2A (model ID, revision),
step level aB0, aC0: DH = 0x04 (family ID), DL = 0x2B (model ID, revision).

2.30.5 Intel i80486SXL CPU

Intel i80486SX CPU with extra features:

SMM (System Management Mode),
stop clock,
power saving features.

static core.

Technology: CMOS.

2.30.6 Intel i80486DX2 P24 CPU

Clock doubled version of the Intel i80486DX CPU.
Intel i80486DX CPU pin compatible.

March 1992.

20/40 MHz.
25/50 MHz: 4000 mW.
33/66 MHz: 4875 mW.

Technology: CMOS.

G4C, G4S.

From June 1993 (Intel i80486DX2-S CPU):

SL Enhanced.

20/40 MHz: SQFP (Shrink Quad Flat Package).
25/50 MHz: iCOMP 231.
33/66 MHz: iCOMP 297.

CPUID: family=0x4, model=0x3.

From November 1993:

SL Enhanced.
Low power: 3.3 V.

20/40 MHz.
25/50 MHz.

From October 1994 (P24D) (not marketed, P24CT Overdrive Processor Pretest Kit for Intel Verification Program (OEM)):

Write-back cache.
Upward pin compatible.
Performance increase: 15 %.

25/50 MHz.
33/66 MHz.

No longer available from fourth quarter 1995.

ID:

step level A0-A2: DH = 0x04 (family ID), DL = 0x32 (model ID, revision),
step level B1: DH = 0x04 (family ID), DL = 0x33 (model ID, revision),
step level aA0, aA1 (SL Enhanced): DH = 0x04 (family ID), DL = 0x34 (model ID, revision),
step level aB0, aC0 (SL Enhanced): DH = 0x04 (family ID), DL = 0x35 (model ID, revision),
step level A (write-back): DH = 0x04 (family ID), DL = 0x36 (model ID, write-through), DL = 0x7X (model ID, write-back).

2.30.7 Intel i80486DX4 P24C CPU

Clock tripled version of the Intel i80486DX CPU.
Selection of doubling/tripling by a pin on the chip (CLKMUL: 0, 1). Connecting this pin with the BREQ pin makes the core running at 2.5 times the external speed (not implemented yet).
Intel i80486DX CPU upward pin compatible.

5 V external, 3.3 V internal: if the motherboard does not provide the 3.3 V power to the CPU, the CPU can be installed using a special socket wired to the 3.3 V output of your PSU (Power Supply Unit); in either case another PSU providing the 3.3 V is needed.

16 kbyte cache.

25/75 MHz max: 3.3 V, March 1994, iCOMP 319.
33/99 MHz max: 51 SPECint92, 27 SPECfp92, 3.3 V, March 1994, iCOMP 435.
Production cancelled for a few months from September 1994 in favor of Intel Pentium CPUs.

Power consumption: 4 W typical.

SL Enhanced Intel i80486DX CPU pin compatible.
Package: 168 pin PGA (Pin Grid Array).

Extra integer multiplier: 5 cycle 16 x 16 multiply.

Package:

168 pin PGA (Pin Grid Array),
208 pin SQFP (Shrink Quad Flat Package).

Technology: 4 layer metal, 0.6 micron biCMOS/CHMOS.
1.6E6 transistors.

ID: step level A: DH = 0x04 (family ID), DL = 0x8X (model ID, revision).

CPUID: step level A: family=0x4, model=0x8.

From October 1994 (Intel i80486DX4WB CPU): write-back cache.
Code: &EW.

Intel i80486DX4 P54LM CPU:

notebooks,
2.5 - 2.9 V,

90 MHz,
100 MHz.

2.30.8 Intel i80486SX2 CPU

Clock doubled version of the Intel i80486SX CPU.

SL Enhanced.

25/50 MHz: March 1994, iCOMP 180.

ID: step level aC0: DH = 0x04 (family ID), DL = 0x5B (model ID, revision).

2.30.9 Intel i80486 CPU announcements

3.3 V versions of existing and new Intel i80486 CPUs.

2.31 AMD Am486 CPU

Originally same core and microcode as Intel i80486 CPUs; currently an own implementation. In between there are CPUs with recompiled 486 microcode.
Intel i80486 CPU instruction compatible.

2.31.1 AMD Am486DX CPU

Intel i80486DX CPU instruction/pin compatible.

April 1993.

33 MHz: 8-33 MHz, 1993.
40 MHz: 8-40 MHz, 1993.

Technology: CMOS.

ID: DH = 0x04 (model ID), DL = 0x12 (model ID, revision).

2.31.2 AMD Am486DXL CPU

Low power version of the AMD Am486DX CPU.

October 1993.

40 MHz.

Technology: CMOS.

ID: DH = 0x04 (model ID), DL = 0x12 (model ID, revision).

2.31.3 AMD Am486DXLV CPU

Low power (SMM: System Management Mode), low voltage (3.0 V) version of the AMD Am486DX CPU.
Static core.

October 1993.

33 MHz: 0-33 MHz, 1993.

Technology: CMOS.

ID: DH = 0x04 (model ID), DL = 0x12 (model ID, revision).

2.31.4 AMD Am486DX2 CPU

Clock doubled version of the AMD Am486DX CPU.

April / October 1993.
From November 1994: 3.3 V.

25/50 MHz: 1993.
33/66 MHz: heatsink required.
40/80 MHz: September 1994, heatsink required.
Some 3.3 V, 66, 80 MHz items are DX4 parts that failed Q.C. at 100 MHz (Malaysia, fab number 25253).

Technology: CMOS.

ID: DH = 0x04 (family ID), DL = 0x02 (model ID, revision).

AMD Enhanced Am486DX2 CPU: CPUID: 0x43x.

2.31.5 AMD Am486DXL2 CPU

Clock doubled version of the AMD Am486DXL CPU.
Low power (SMM: System Management Mode).

AMD core/microcode.

33/66 MHz.
40/80 MHz.

Technology: CMOS.

ID: DH = 0x04 (family ID), DL = 0x32 (model ID, revision).

2.31.6 AMD Am486DX4 CPU

Clock tripled version of the AMD Am486DX CPU.
Intel i80486DX4 CPU pin compatible.
Selection of doubling/tripling by a pin on the chip.

8 kbyte cache: write-through.

33/99 MHz: 3.3 V, September 1994, heatsink + fan required.

Technology: 0.5 micron, 3 layer CMOS.

ID: DH = 0x04 (family ID). DL = 0x32 (model ID, revision).

AMD Am80486DX4-xxxNT8T CPU.
AMD Am80486DX4-xxxNV8T CPU.

Enhanced AMD Am486DX4 CPU (AMD Am80486DX4-xxxSV8B CPU):

SL Enhanced,
write-back cache,
3.3 V:

33/99 MHz,
40/120 MHz,

package:
- 169 pin PGA (Pin Grid Array),
- 208 pin SQFP,

AMD Enhanced Am486DX4 CPU: CPUID: 0x48x,
AMD Enhanced Am486DX4W CPU: CPUID: 0x49x.

Label: A 80486DX4-100 SV8B:

S: SMM (System Management Mode), N: standard,
V: 3.45 V, _: standard,
8: 8 kbyte cache, 16: 16 kbyte cache,
B: write-back cache, T: write-through cache.

2.31.7 AMD Am486SX CPU

Intel i80486SX CPU instruction/pin compatible.

AMD microcode.

July 1993.

33 MHz: 1993.
40 MHz: 1993.

Technology: CMOS.

2.31.8 AMD Am486SXLV CPU

Low power (SMM: System Management Mode), low voltage (3.0 V) version of the AMD Am486SX CPU.
Static core.

AMD microcode.

July 1993.

33 MHz.

Technology: CMOS.

2.31.9 AMD Am486SX2 CPU

Clock doubled version of the AMD Am486SX CPU.

25/50 MHz: February 1994.
33/66 MHz: April 1994.

2.31.10 AMD Am486SE CPU

Embedded static version of the AMD Am486SX CPU.

25 MHz: 1995.
33 MHz: 1995.

Package: CGM168.

AMD Embedded Processors E86 Family.

2.31.11 AMD Am5x86 CPU

Clock quadrupled Enhanced 486.
SL Enhanced Intel i80486DX2 CPU (P24D) pin compatible.

16 kbyte cache: write-back.

33/133 MHz (AMD Am5x86-P75, AMD X5-133ADW): November 1995.
40/160 MHz.

3.45 V.

Label: Amd 5x86-P75 ADW:

A: PGA (Pin Grid Array), S: SQFP,
D: 3.45 V, F: 3.3 V,
W: case temperature 55 C, Y: 75 C, Z: 85 C.

2.32 IBM 80486 CPU

Intel i80486 CPU instruction compatible.

2.32.1 IBM 80486DX CPU

Intel i80486DX CPU instruction/pin compatible.

Technology: CMOS.

2.32.2 IBM 80486SX CPU

Intel i80486SX CPU instruction/pin compatible.

16 kbyte cache.

Technology: CMOS.

2.32.3 IBM 80486BLDX2 CPU (Blue Lightning)

33/66 MHz: Cyrix FasCache Cx486DX2-V-66 CPU.
40/80 MHz: Cyrix FasCache Cx486DX2-V-80 CPU.

ID: DH = 0xA4 (family ID), DL = 0x80 (model ID, revision).

2.33 Cyrix Cx486 CPU

2.33.1 Cyrix FasCache Cx486D CPU

Intel i80486 CPU instruction compatible, no build-in FPU (Floating Point Unit).
Can piggy-back a Cyrix Cx487S NPX.

2 kbyte cache: write back.

Intel i80486SX CPU upward pin compatible.

On-chip ventilator.

40 MHz: 1993.

Technology: CMOS.

Cyrix M5 CPU.

ID: DH = 0x00 (family ID), DL = 0x05 (model ID).

2.33.2 Cyrix FasCache Cx486S CPU

Intel i80486 CPU instruction compatible, no build-in FPU (Floating Point Unit).
Low Power: SMM (System Management Mode).
Static core.

2 kbyte cache: write back.

Intel i80486SX CPU upward pin compatible.

May 1993.

33 MHz.
40 MHz: 1993.
50 MHz.

Technology: CMOS.

Cyrix M5 CPU.

ID: DH = 0x00 (family ID), DL = 0x05 (model ID).

DIR0 register: 0x10.

2.33.3 Cyrix FasCache Cx486S/e CPU

Low power (SMM: System Management Mode) version of the Cyrix FasCache Cx486S CPU. Static core.

DIR0 register: 0x12.

2.33.4 Cyrix FasCache Cx486S-V CPU

Low voltage (3.3 V) version of the Cyrix FasCache 486S CPU.

May 1993.

25 MHz.
33 MHz.

Technology: CMOS.

DIR0 register: 0x10.

2.33.5 Cyrix FasCache Cx486S2 CPU

Clock doubled version of the Cyrix FasCache 486S CPU.

October 1993.

20/40 MHz.
25/50 MHz.

Technology: CMOS.

DIR0 register: 0x11.

2.33.6 Cyrix FasCache Cx486S2/e CPU

Low power (SMM: System Management Mode) version of the Cyrix FasCache Cx486S2 CPU.
Static core.

DIR0 register: 0x13.

2.33.7 Cyrix FasCache Cx486S2-V CPU

Low voltage (3.3 V) version of the Cyrix FasCache Cx486S2 CPU.

October 1993.

20/40 MHz.
25/50 MHz.

Technology: CMOS.

DIR0 register: 0x11.

Cyrix FasCache Cx486DX/Cx486DX2 CPU FP bug: when a register load instruction is followed by an instruction that clears the FP status register (FCLEX), and the memory location being referenced is not in the CPU's internal cache, the external memory bus cycle is aborted by the FCLEX instruction and the register is not loaded properly.
Since this code sequence is very unlikely to occur in any software, the bug will probably not be fixed at all.